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| (R) ISL28196, ISL28197 Data Sheet September 29, 2008 FN6152.4 Ultra-Small, 800nA and 2.5A Single Supply, Rail-to-Rail Input/Output (RRIO) Comparators The ISL28196 and ISL28197 are micropower comparators optimized for low-power applications. The parts are designed for single-supply operation from 1.8V to 5.5V. The ISL28197 typically consumes 800nA of supply current and the ISL28196 typically consumes 2.5A of supply current. Both parts feature rail-to-rail input and output swing (RRIO), allowing for maximum battery usage. The ISL28196 features a propagation delay of 150s and the ISL28197 features a propagation delay of 0.6ms. Equipped with an ENABLE pin (EN), both parts draw typically 2nA when off. The combination of small footprint, low power, single supply, and rail-to-rail operation makes them ideally suited for all battery operated devices. Features * Typical Supply Current 800nA (ISL28197) * Typical Supply Current 2.5A (ISL28196) * Ultra-Low Single-Supply Operation Down to +1.8V * Rail-to-Rail Input/Output Voltage Range (RRIO) * 150s Typical Propagation Delay (ISL28196) * 0.6ms Typical Propagation Delay (ISL28197) * ENABLE Pin Feature * Push-Pull Output * -40C to +125C Operation * Pb-Free (RoHS Compliant) Applications * 2-Cell Alkaline Battery-Powered/Portable Systems * Window Comparators * Threshold Detectors/Discriminators Pinouts ISL28196, ISL28197 (6 LD SOT-23) TOP VIEW OUT 1 GND 2 IN+ 3 6 V+ 5 EN 4 IN- Ordering Information PART NUMBER ISL28196FHZ-T7* (Note 1) PART MARKING GABM PACKAGE Tape & Reel (Pb-Free) 6 Ld SOT-23 PKG. DWG. # MDP0038 +- ISL28196, ISL28197 (6 LD 1.6X1.6X0.5 TDFN) TOP VIEW IN- 1 +GND 2 IN+ 3 6 V+ 5 EN 4 OUT ISL28196FRUZ-T7* M5 (Note 2) ISL28197FHZ-T7* (Note 1) GABN 6 Ld 1.6x1.6x0.5 TDFN L6.1.6x1.6A 6 Ld SOT-23 MDP0038 ISL28197FRUZ-T7* M6 (Note 2) 6 Ld 1.6x1.6x0.5 TDFN L6.1.6x1.6A *Please refer to TB347 for details on reel specifications. NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pbfree material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. These Intersil Pb-free plastic packaged products employ special Pbfree material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL28196, ISL28197 Absolute Maximum Ratings (TA = +25C) Supply Voltage (V+, V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.75V Supply Turn On Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . 1V/s Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Differential Input Voltage . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V Thermal Information Thermal Resistance (Typical, Note 3) JA (C/W) 6 Ld SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . . 230 6 Ld TDFN Package . . . . . . . . . . . . . . . . . . . . . . . 117.52 Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . . . . . .Indefinite Ambient Operating Temperature Range . . . . . . . . .-40C to +125C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . +125C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, Therefore TJ = TC = TA Electrical Specifications V+ = 5V, V- = 0V, VCM = 2.5V, TA = +25C, unless otherwise specified. Boldface limits apply over -40C to +125C. DESCRIPTION CONDITIONS MIN (Note 4) -2 -2.5 -60 -100 -80 -150 Established by CMRR test VCM = 0.5V to 3.5V VCM = 0V to 5V 0 70 70 60 70 70 100 35 4.930 4.950 2.5 0.8 2 1.8 5 4.0 4.5 1.6 2.0 20 50 5.5 70 100 TYP -0.1 10 15 MAX (Note 4) 2 2.5 60 100 80 150 5 UNIT mV pA pA V dB dB dB mV V A A nA V pF PARAMETER VOS IOS IB CMIR CMRR Input Offset Voltage Input Offset Current Input Bias Current Common Mode Input Range Common-Mode Rejection Ratio PSRR VOUT Power Supply Rejection Ratio Maximum Output Voltage Swing RL terminated to V+/2 Supply Current, Enabled V+ = 1.8V to 5.5V Output low, RL = 10k Output high, RL = 10k ISL28196 ISL28197 IS,ON IS,OFF VSUPPLY CIN Supply Current, Disabled Supply Voltage Range Input Capacitance EN = 0.4V ENABLE INPUT VINH VINL IENH IENL Enable Pin High Level Enable Pin Low Level Enable Pin Input Current Enable Pin Input Current VEN = 5V VEN = 0V 30 30 (V+)x(0.8) 0.4 150 200 150 200 V V nA nA 2 FN6152.4 September 29, 2008 ISL28196, ISL28197 Electrical Specifications V+ = 5V, V- = 0V, VCM = 2.5V, TA = +25C, unless otherwise specified. Boldface limits apply over -40C to +125C. (Continued) DESCRIPTION CONDITIONS MIN (Note 4) TYP MAX (Note 4) UNIT PARAMETER TIMING tPD tPD tR/tF ISL28196 Propagation Delay Low to High and High to Low CL = 10pF, 20mV Overdrive ISL28197 Propagation Delay Low to High and High to Low CL = 10pF, 1.5V Overdrive ISL28196 Rise/Fall Time ISL28197 Rise/Fall Time CL = 10pF CL = 10pF 150 0.625 9 35 300 1.3 18 70 s ms s s NOTE: 4. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, unless otherwise specified. 164 162 SUPPLY CURRENT (nA) 160 158 156 154 152 150 148 146 1.5 2.0 2.5 3.0 3.5 4.0 SUPPLY VOLTAGE (V) 4.5 5.0 670 1.5 2.0 2.5 3.0 3.5 4.0 SUPPLY VOLTAGE (V) 4.5 5.0 RL = INF 720 SUPPLY CURRENT (nA) 710 700 690 680 730 RL = INF FIGURE 1. ISL28196 SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 2. ISL28197 SUPPLY CURRENT vs SUPPLY VOLTAGE 400 350 300 DELAY (s) DELAY (s) 250 200 150 100 50 0 1.5 2.0 OD = 100mV RL TO V+ OD = 20mV RL TO GND RL TO V+ RL = 10k RL TO GND 1200 RL = 10k 1000 800 OD = 20mV 600 400 200 0 2.5 3.0 3.5 4.0 SUPPLY VOLTAGE (V) 4.5 5.0 1.5 2.0 2.5 3.0 3.5 4.0 SUPPLY VOLTAGE (V) 4.5 5.0 OD = 100mV RL TO V+ RL TO GND RL TO V+ RL TO GND FIGURE 3. ISL28196 PROP DELAY vs SUPPLY VOLTAGE (RISING EDGE) FIGURE 4. ISL28197 PROP DELAY vs SUPPLY VOLTAGE (RISING EDGE) 3 FN6152.4 September 29, 2008 ISL28196, ISL28197 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, unless otherwise specified. 350 RL = 10k 300 250 DELAY (s) OD = 20mV 200 150 100 50 0 1.5 OD = 100mV 2.0 2.5 3.0 3.5 4.0 SUPPLY VOLTAGE (V) 4.5 5.0 RL TO GND 200 OD = 100mV 0 1.5 2.0 2.5 3.0 3.5 4.0 SUPPLY VOLTAGE (V) 4.5 5.0 RL TO GND RL TO V+ RL TO V+ 1000 800 600 400 RL TO GND 1200 RL = 10k RL TO V+ (Continued) FIGURE 5. ISL28196 PROP DELAY vs SUPPLY VOLTAGE (FALLING EDGE) FIGURE 6. ISL28197 PROP DELAY vs SUPPLY VOLTAGE (FALLING EDGE) 900 800 700 DELAY (s) DELAY (s) 600 500 400 300 200 100 0 1 10 100 1000 OVERDRIVE (mV) V+ = 2V RL TO GND RL TO V+ V+ = 5V RL = 10k DELAY (s) OD = 20mV RL TO GND RL TO V+ 3500 3000 2500 2000 1500 1000 500 0 1 10 100 OVERDRIVE (mV) 1000 RL TO GND RL TO V+ V+ = 2V V+ = 5V RL = 10k FIGURE 7. ISL28196 PROP DELAY vs OVERDRIVE (RISING EDGE) FIGURE 8. ISL28197 PROP DELAY vs OVERDRIVE (RISING EDGE) 900 800 700 DELAY (s) 600 DELAY (s) 500 400 300 200 RL TO GND RL TO V+ V+ = 5V RL = 10k 3000 V+ = 5V 2500 2000 1500 1000 500 RL TO GND RL TO V+ RL = 10k V+ = 2V 100 0 1 V+ = 2V 0 10 100 1000 1 10 100 1000 OVERDRIVE (mV) OVERDRIVE (mV) FIGURE 9. ISL28196 PROP DELAY vs OVERDRIVE (FALLING EDGE) FIGURE 10. ISL28197 PROP DELAY vs OVERDRIVE (FALLING EDGE) 4 FN6152.4 September 29, 2008 ISL28196, ISL28197 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, unless otherwise specified. 25 RL = 10 OUTPUT CURRENT (mA) 20 SINKING 15 SOURCING OUTPUT CURRENT (mA) 20 SINKING 15 SOURCING 25 RL = 10 (Continued) 10 10 5 5 0 1.0 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) FIGURE 11. ISL28196 SHORT CIRCUIT CURRENT vs SUPPLY VOLTAGE FIGURE 12. ISL28197 SHORT CIRCUIT CURRENT vs SUPPLY VOLTAGE 3.0 2.8 ENABLE THRESHOLD (V) 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 ENABLE THRESHOLD (V) 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) FIGURE 13. ISL28196 ENABLE THRESHOLD VOLTAGE vs SUPPLY VOLTAGE FIGURE 14. ISL28197 ENABLE THRESHOLD VOLTAGE vs SUPPLY VOLTAGE 100 ENABLE TO OUTPUT DELAY (ms) 80 ENABLE TO OUTPUT DELAY (ms) 90 80 70 60 50 40 30 20 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 70 60 50 40 30 20 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) FIGURE 15. ISL28196 ENABLE TO OUTPUT DELAY TIME vs SUPPLY VOLTAGE FIGURE 16. ISL28197 ENABLE TO OUTPUT DELAY TIME vs SUPPLY VOLTAGE 5 FN6152.4 September 29, 2008 ISL28196, ISL28197 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, unless otherwise specified. 1000 DISABLE TO OUTPUT DELAY (ns) DISABLE TO OUTPUT DELAY (ns) 950 900 850 800 750 700 650 600 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1500 1400 1300 1200 1100 1000 900 800 700 600 1.5 2.0 SUPPLY VOLTAGE (V) 2.5 3.0 3.5 4.0 SUPPLY VOLTAGE (V) 4.5 5.0 (Continued) FIGURE 17. ISL28196 ENABLE LOW TO OUTPUT TURN-OFF TIME vs SUPPLY VOLTAGE FIGURE 18. ISL28197 ENABLE LOW TO OUTPUT TURN-OFF TIME vs SUPPLY VOLTAGE 4.5 4.0 SUPPLY CURRENT (A) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 N = 1000 1.8 MAX SUPPLY CURRENT (A) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 N = 1000 MAX MEDIAN MEDIAN MIN MIN -40 -20 0 20 40 60 80 100 120 0 -40 -20 0 TEMPERATURE (C) 20 40 60 80 TEMPERATURE (C) 100 120 FIGURE 19. ISL28196 SUPPLY CURRENT vs TEMPERATURE, V+, V- = 2.5V FIGURE 20. ISL28197 SUPPLY CURRENT vs TEMPERATURE, V+, V- = 2.5V 90 80 70 60 IBIAS+ (pA) N = 1000 100 80 MAX 60 IBIAS+ (pA) N = 1000 MEDIAN MAX 50 40 30 20 MEDIAN 40 20 MIN 0 10 0 -40 -20 0 20 40 60 MIN 80 100 120 -20 -40 -20 0 20 40 60 80 TEMPERATURE (C) 100 120 TEMPERATURE (C) FIGURE 21. ISL28196 IBIAS+ vs TEMPERATURE, V+, V- = 2.5V FIGURE 22. ISL28197 IBIAS+ vs TEMPERATURE, V+, V- = 2.5V 6 FN6152.4 September 29, 2008 ISL28196, ISL28197 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, unless otherwise specified. 120 N = 1000 100 80 IBIAS- (pA) MAX 60 40 20 MIN 0 -40 -20 0 20 40 60 80 100 120 0 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) TEMPERATURE (C) MEDIAN IBIAS- (pA) 100 MAX 80 MEDIAN 60 40 20 MIN 120 N = 1000 (Continued) FIGURE 23. ISL28196 IBIAS- vs TEMPERATURE, V+, V- = 2.5V FIGURE 24. ISL28197 IBIAS- vs TEMPERATURE, V+, V- = 2.5V 70 N = 1000 60 50 IOS (pA) 40 30 20 MEDIAN 10 MIN 0 -40 -20 0 20 40 60 80 100 120 MAX IOS (pA) 50 45 40 35 30 25 20 15 10 5 0 -40 -20 0 20 40 60 80 MIN 100 120 MEDIAN MAX N = 1000 TEMPERATURE (C) TEMPERATURE (C) FIGURE 25. ISL28196 IOS vs TEMPERATURE, V+, V- = 2.5V FIGURE 26. ISL28197 IOS vs TEMPERATURE, V+, V- = 2.5V 3 2 N = 1000 MAX 3 2 N = 1000 MAX 1 VOS (V) 0 MEDIAN -1 -2 MIN -3 -40 -20 0 20 40 60 80 100 120 VOS (V) 1 0 MEDIAN -1 -2 MIN -3 -40 -20 0 20 40 60 80 TEMPERATURE (C) 100 120 TEMPERATURE (C) FIGURE 27. ISL28196 VOS vs TEMPERATURE, V+, V- = 2.5V VIN = 2.5V FIGURE 28. ISL28197 VOS vs TEMPERATURE, V+, V- = 2.5V VIN = 2.5V 7 FN6152.4 September 29, 2008 ISL28196, ISL28197 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, unless otherwise specified. 105 100 95 CMRR (dB) CMRR (dB) 90 85 MIN 80 75 70 -40 MEDIAN N = 1000 105 MAX 100 95 90 85 80 MIN 75 70 -40 MEDIAN N = 1000 (Continued) MAX -20 0 20 40 60 80 100 120 -20 0 20 40 60 80 100 120 TEMPERATURE (C) TEMPERATURE (C) FIGURE 29. ISL28196 CMRR vs TEMPERATURE, VCM = 0.5V TO 3.5, V+, V- = 2.5V FIGURE 30. ISL28197 CMRR vs TEMPERATURE, VCM = 0.5V TO 3.5, V+, V- = 2.5V 110 105 N = 1000 MAX 110 105 100 PSRR (dB) 95 90 85 80 MIN 75 60 80 100 120 N = 1000 MAX 100 PSRR (dB) 95 90 MEDIAN 85 80 75 70 -40 -20 0 20 MEDIAN MIN 40 70 -40 -20 0 TEMPERATURE (C) 20 40 60 80 TEMPERATURE (C) 100 120 FIGURE 31. ISL28196 PSRR vs TEMPERATURE, V+, V- = 0.9V TO 2.5V FIGURE 32. ISL28197 PSRR vs TEMPERATURE, V+, V- = 0.9V TO 2.5V 4.956 4.954 4.952 4.950 VOUT (V) N = 1000 MAX 4.955 4.954 4.953 4.952 MIN MEDIAN VOUT (V) 4.951 4.950 4.949 4.948 4.947 4.946 N = 1000 4.948 4.946 4.944 4.942 4.940 4.938 4.936 -40 -20 0 MAX MEDIAN MIN 20 40 60 80 100 120 4.945 -40 -20 0 TEMPERATURE (C) 20 40 60 80 TEMPERATURE (C) 100 120 FIGURE 33. ISL28196 VOUT HIGH vs TEMPERATURE, V+, V- = 2.5V, RL = 10k FIGURE 34. ISL28197 VOUT HIGH vs TEMPERATURE, V+, V- = 2.5V, RL = 10k 8 FN6152.4 September 29, 2008 ISL28196, ISL28197 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, unless otherwise specified. 50 N = 1000 45 40 VOUT (mV) 35 30 25 20 MIN 15 -40 -20 0 20 40 60 80 TEMPERATURE (C) 100 120 25 -40 -20 0 VOUT (mV) MAX 37 MAX 35 33 31 MEDIAN 29 27 MIN 20 40 60 80 TEMPERATURE (C) 100 120 39 N = 1000 (Continued) MEDIAN FIGURE 35. ISL28196 VOUT LOW vs TEMPERATURE, V+, V- = 2.5V, RL = 10k FIGURE 36. ISL28197 VOUT LOW vs TEMPERATURE, V+, V- = 2.5V, RL = 10k 270 N = 1000 250 + PROP DELAY (s) 230 210 190 170 150 -40 MEDIAN + PROP DELAY (s) MAX 1750 1550 N = 1000 MAX 1350 1150 950 750 550 350 MIN -20 0 20 40 60 80 TEMPERATURE (C) 100 120 MEDIAN MIN -20 0 20 40 60 80 TEMPERATURE (C) 100 120 150 -40 FIGURE 37. ISL28196 POSITIVE PROP DELAY vs TEMPERATURE 50% TO 20%, V+ = 5V FIGURE 38. ISL28197 POSITIVE PROP DELAY vs TEMPERATURE 50% TO 20%, V+ = 5V 220 N = 1000 200 - PROP DELAY (s) - PROP DELAY (s) MAX 180 160 140 120 MIN 100 -40 -20 0 20 40 60 80 TEMPERATURE (C) 100 120 MEDIAN 1700 1500 1300 N = 1000 MAX 1100 900 700 500 300 MIN 100 -40 -20 0 20 40 60 80 TEMPERATURE (C) 100 120 MEDIAN FIGURE 39. ISL28196 NEGATIVE PROP DELAY vs TEMPERATURE 50% TO 20%, V+ = 5V FIGURE 40. ISL28197 NEGATIVE PROP DELAY vs TEMPERATURE 50% TO 20%, V+ = 5V 9 FN6152.4 September 29, 2008 ISL28196, ISL28197 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, unless otherwise specified. 8.0 N = 1000 7.5 + PROP DELAY (s) 7.0 6.5 6.0 5.5 5.0 MIN 4.5 -40 -20 0 20 40 60 80 TEMPERATURE (C) 100 120 MEDIAN MAX + PROP DELAY (s) 54.5 49.5 44.5 39.5 34.5 29.5 24.5 19.5 14.5 9.5 4.5 -40 -20 0 MEDIAN MIN MAX (Continued) N = 1000 20 40 60 80 TEMPERATURE (C) 100 120 FIGURE 41. ISL28196 FALL TIME vs TEMPERATURE 20% TO 80%, V+ = 5V FIGURE 42. ISL28197 FALL TIME vs TEMPERATURE 20% TO 80%, V+ = 5V Pin Descriptions ISL28196, ISL28196, ISL28197 ISL28197 (6 LD SOT-23) (6 LD TDFN) 1 2 3 4 5 6 4 2 3 1 5 6 EQUIVALENT CIRCUIT Circuit 3 Circuit 4 Circuit 1 Circuit 1 Circuit 2 Circuit 4 Comparator output GROUND terminal Comparator non-inverting input Comparator inverting input Comparator enable pin; Logic "1" selects the enabled state: Logic "0" selects the disabled state Positive power supply V+ V+ INLOGIC PIN VCIRCUIT 2 CIRCUIT 3 V+ 100 OUT VVCIRCUIT 4 PIN NAME OUT GND IN+ INEN V+ DESCRIPTION V+ CAPACITIVELY COUPLED ESD CLAMP IN+ V- CIRCUIT 1 Applications Information Introduction The ISL28196 and ISL28197 are CMOS rail-to-rail input and output (RRIO) micropower comparators. These devices are designed to operate from single supply (1.8V to 5.5V) and have an input common mode range that extends to the positive rail and to the negative supply rail for true rail-to-rail performance. The CMOS output can swing within tens of millivolts to the rails. Featuring worst case maximum supply currents of only 4.5A and 2A for the ISL28196 and ISL28197 respectively, these comparators are ideally suited for solar and battery powered applications. Input Protection All input terminals have internal ESD protection diodes to both positive and negative supply rails, limiting the input voltage to within one diode beyond the supply rails. Both the ISL28196 and ISL28197 have a maximum input differential voltage that extends beyond the rails (+V + 0.5V to -V - 0.5V). Rail-to-Rail Output A pair of complementary MOSFET devices are used to achieve the rail-to-rail output swing. The NMOS sinks current to swing the output in the negative direction. The PMOS sources current to swing the output in the positive direction. The ISL28196 and ISL28197 with a 100k load will swing to within 6mV of the positive supply rail and within 3mV of ground. 10 FN6152.4 September 29, 2008 ISL28196, ISL28197 Break-Before-Make Operation of the Output The output circuit has a break-before-make response. This means that the P-Channel turns off before the N-Channel turns on during a high to low transition of the output (reference Figure 43). Likewise, the N-Channel turns off before the P-Channel turns on during a low to high transition. This results in different propagation delay times depending upon where the output load resistor is tied to. If the load resistor is tied to ground, (Figure 44A) then the propagation delay is controlled by the P-Channel. For a high to low transition the propagation delay does not include the additional break-before-make time because the load resistor will pull the output low once the P-Channel has turned off. BREAK-BEFORE-MAKE If the load resistor is tied to V+ (Figure 44B) then the propagation delay is controlled by the N-Channel. For this condition, the additional delay time is added to the high to low transition because the output won't pull low until the N-Channel turns on. Figures 3 through 10 show the differences in propagation delay depending upon where the load is tied. Propagation Delay The input to output propagation delay has a dependency on power supply voltage, overdrive and whether the output is sourcing or sinking current. Figures 3 and 5 show a decreasing time propagation delay vs supply voltage for the ISL28196 and Figure 4 shows a similar behavior for the ISL28197. The output break-before-make mechanism results in a difference in propagation delay, depending on whether the output stage NMOS and PMOS are sourcing or sinking current. This delay difference is shown in the figures as a function of where the load is terminated (+V or -V) and also as a function of supply voltage. The dependence of propagation delay as a function of power supply voltage and input overdrive (from 5mV to 1V) is shown in Figures 7 and 9 for the ISL28196, and Figures 8 and 10 for the ISL28197. P-CH OFF ISL28196 AND ISL28197 OUTPUT STAGE P-CH ON P-CH ON v+ P-CHANNEL N-CH OFF N-CH OFF VOUT N-CHANNEL N-CH ON Enable Feature Both parts offer an EN pin, which enables the device when pulled high. The enable threshold is referenced to the -V terminal and has a level proportional to the total supply voltage (reference Figures 13 and 14 for EN Threshold vs Supply Voltage). The enable circuit has a delay time that changes as a function of supply voltage. Figures 23 through 26 show the effect of supply voltage on the enable and disable times. For supply voltages less than 3V, it is recommended that the user account for the increase enable/disable delay time. In the disabled state (output in a high impedance state), the supply current is reduced to a typical of only 2nA. By disabling the devices, multiple parts can be connected together as a MUX. In this configuration, the outputs are tied together in parallel and a channel can be selected by the EN pin. The EN pin should never be left floating. The EN pin should be connnected directly to the V+ supply when not in use. FIGURE 43. MAKE-BEFORE-BREAK ACTION OF THE OUTPUT STAGE During the low to high transition, however, if the load resistor is tied to ground, then the additional break-before-make time is added to the propagation delay time because the output won't pull high until the P-Channel turns on. V+ + RL VOUT FIGURE 44A. RL TO GND V+ Proper Layout Maximizes Performance + RL VOUT FIGURE 44B. RL TO V+ FIGURE 44. CONNECTION OF RL TO GND AND V+ To achieve the maximum performance of the high input impedance, care should be taken in the circuit board layout. The PC board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. When input leakage current is a concern, the use of guard rings around the comparator inputs will further reduce leakage currents. 11 FN6152.4 September 29, 2008 ISL28196, ISL28197 Power Dissipation It is possible to exceed the +150C maximum junction temperatures under certain load and power-supply conditions. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related in Equation 1: T JMAX = T MAX + ( JA xPD MAXTOTAL ) (EQ. 1) where: * PDMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PDMAX) * PDMAX for each amplifier can be calculated as shown in Equation 2: V OUTMAX PD MAX = 2*V S x I SMAX + ( V S - V OUTMAX ) x --------------------------RL (EQ. 2) where: * TMAX = Maximum ambient temperature * JA = Thermal resistance of the package * PDMAX = Maximum power dissipation of 1 amplifier * VS = Supply voltage (Magnitude of V+ and V-) * IMAX = Maximum supply current of 1 amplifier * VOUTMAX = Maximum output voltage swing of the application * RL = Load resistance 12 FN6152.4 September 29, 2008 ISL28196, ISL28197 Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN) E 6 4 A A B L6.1.6x1.6A 6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL MIN 0.45 NOMINAL 0.50 0.127 REF 0.15 1.55 0.40 1.55 0.95 0.20 1.60 0.45 1.60 1.00 0.50 BSC 0.25 0.30 0.35 0.25 1.65 0.50 1.65 1.05 MAX 0.55 0.05 NOTES 4 4 Rev. 1 6/06 NOTES: 1. Dimensions are in mm. Angles in degrees. 2. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall not exceed 0.08mm. PIN 1 REFERENCE 2X 0.15 C 1 2X 0.15 C TOP VIEW e 1.00 REF 4 6 3 D A A1 A3 A1 b D D2 L D2 CO.2 DAP SIZE 1.30 x 0.76 E E2 e L 3 E2 1 b 6X 0.10 M C A B BOTTOM VIEW DETAIL A 0.10 C 6X 0.08 C A3 SIDE VIEW C SEATING PLANE 3. Warpage shall not exceed 0.10mm. 4. Package length/package width are considered as special characteristics. 5. JEDEC Reference MO-229. 6. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389. 0.1270.008 0.127 +0.058 -0.008 TERMINAL THICKNESS A1 DETAIL A 0.25 0.50 1.00 0.45 1.00 2.00 0.30 1.25 LAND PATTERN 6 13 FN6152.4 September 29, 2008 ISL28196, ISL28197 SOT-23 Package Family e1 A N 6 4 MDP0038 D SOT-23 PACKAGE FAMILY MILLIMETERS SYMBOL A A1 SOT23-5 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 5 SOT23-6 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 6 TOLERANCE MAX 0.05 0.15 0.05 0.06 Basic Basic Basic Basic Basic 0.10 Reference Reference Rev. F 2/07 NOTES: E1 2 3 E A2 b c 0.20 C 0.15 C D 2X 5 e B b NX 1 2 3 2X 0.20 M C A-B D D E E1 e e1 L L1 N 0.15 C A-B 2X C D 1 3 A2 SEATING PLANE 0.10 C NX A1 1. Plastic or metal protrusions of 0.25mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. This dimension is measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only). (L1) H 6. SOT23-5 version has no center lead (shown as a dashed line). A GAUGE PLANE c L 0 +3 -0 0.25 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 14 FN6152.4 September 29, 2008 |
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